1. The Field of the Invention
The present invention relates to methods for forming a local interconnect on a semiconductor substrate. More particularly, the present invention relates to methods of forming a local interconnect from refractory metal silicides on a semiconductor substrate. The method of the present invention is particularly useful in forming self-aligned titanium silicide local interconnects in a manner that is less complex and more reliable than conventional methods.
2. The Relevant Technology
Integrated circuits are currently manufactured by an elaborate process in which a multitude of electronic devices are integrally formed on a small silicon wafer. The conventional electronic devices which are formed on the silicon wafer include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these electronic devices are formed on a single silicon wafer.
One step in the process of manufacturing integrated circuits is to provide electrical communication between the discrete electronic devices on the integrated circuit. Structures for electrically interconnecting electronic devices or portions of electronic devices are broadly referred to as contacts. One form of contact for electrically interconnecting electronic devices on an integrated circuit wafer is with a local interconnect. The local interconnect generally comprises a region of conducting material formed between the electronic devices or portions of the electronic devices and allows for an electrical current to be delivered to and from the electronic devices or portions thereof so that the integrated circuit can perform its intended function.
The computer industry is constantly under market demand to increase the speed at which integrated circuits operate, to decrease the size of the integrated circuits, and to reduce the price of the integrated circuits. To accomplish this task, the electronic devices on a silicon wafer are continually being increased in number and decreased in dimension in a process known as miniaturization. In turn, the dimensions of the local interconnect must also be decreased.
The existing conventional technology for forming local interconnects is currently a limiting factor in the miniaturization of integrated circuits. Also, certain shortcomings in the conventional technology for forming local interconnects place limitations on the speed and efficiency of integrated circuits. The conventional technology also substantially increases the cost of forming the integrated circuits.
A currently technology being used for forming local interconnects is a method involving the self-aligned formation of titanium silicide. The resulting structure is known as titanium salicide. This conventional method for forming a local interconnect from titanium salicide is illustrated in FIGS. 1 through 7 and will be briefly discussed in order to better illustrate the shortcomings of the conventional method.
As shown in FIG. 1, the first step in the conventional method for forming a titanium salicide local interconnect is to provide the electronic devices that are to be placed in electrical communication by the local interconnect. Thus, shown in FIG. 1 is a silicon substrate 10 of an in-process integrated circuit wafer having formed thereon field oxide spacers 12 as well as active regions 14a, 14b, and 14c. Also formed thereon are a first gate region 18a, second gate region 16, and third gate region 18b. Each of gate region 18a, 18b, and 16 is formed with an integral pair of spacers 20 formed at its outer edges. In the depicted embodiment, shown as a representative example of the use of local interconnects, second gate region 16 forms the gate region of a MOS transistor and first and third gate regions 18a and 18b form word lines of a MOS memory device and are located atop field oxide spacers 12. In the depicted embodiment of FIGS. 1 through 7, three local interconnects are being constructed for use in electrically connecting gate regions 16, 18a, hand 18b with adjoining active regions 14a, 14b, and 14c respectively.
FIG. 2 depicts a subsequent step of the conventional method of forming local interconnects, wherein a thin titanium layer 22 is formed over the surface of gate regions 16, 18a, and 18b, and active regions 14a, 14b, and 14c. Thin titanium layer 22 is typically formed with a deposition process such as physical vapor deposition (PVD).
Thereafter, as shown in FIG. 3, a polysilicon layer 24 is formed over the top of thin titanium layer 22. Conventional methods of depositing polysilicon layer 24 typically involve a process of decomposition of a precursor material such as disilane.
FIG. 4 illustrates a subsequent step of the conventional method involving the formation of a photoresist mask 26 over portions of polysilicon layer 24 where the local interconnects are to be formed. Photoresist mask 26 is formed using photolithography.
Once photoresist mask 26 is in place, the portions of polysilicon layer 24 which are not covered by photoresist mask 26 are etched. The etch process typically comprises a vapor or "dry" etch using an etchant that etches silicon at a high rate, but optimally, is selective to titanium. The result of the etch process is showed in FIG. 5. As shown therein, titanium layer 22 remains, but polysilicon layer 24 remains only over the portions where photoresist mask 26 covered polysilicon layer 24.
After etching polysilicon layer 24, photoresist mask 26 is removed. The in-process integrated circuit wafer is then annealed in an atmosphere of gaseous nitrogen with a process of rapid thermal annealing. As depicted in FIG. 6, the rapid thermal anneal converts the portions of thin titanium layer 22 which are covered with polysilicon silicon layer 24 into regions of titanium silicide 28. The portions of thin titanium layer 24 which are not covered with polysilicon layer 24 but which are exposed by the etching of polysilicon layer 24 are converted into regions of titanium nitride 30.
As a final step in the conventional method, an etch is conducted to remove the portions of thin titanium layer 22 which have been converted to regions of titanium nitride 30. The titanium nitride etch is conducted with an etchant which is selective to titanium silicide, and results in the structure of FIG. 7, wherein patterned regions of titanium silicide 28 remain. The patterned regions of titanium silicide 28 will then be used to form completed titanium salicide local interconnects, providing pathways for electrical communication linking gate regions 18a, 16, and 18b with active regions 14a, 14b, and 14c, respectively.
One shortcoming involved with this conventional method of forming titanium salicide local interconnects is the inherent complex nature of the method. The method involves numerous intricate steps that add time and expense to the integrated circuit manufacturing process, thereby elevating the cost of the finished integrated circuit.
A further shortcoming of the conventional method involves the process of etching polysilicon layer 24. One undesirable side effect of the polysilicon etching process is that the etchant typically undercuts photoresist mask 26, thus etching into portions of polysilicon layer 24 which are covered and are not intended to be etched. The undercutting thus alters the critical dimensions of the etch.
Another drawback to the polysilicon etching process of the conventional method is that it has difficulty in maintaining a high selectivity to titanium. Conventional polysilicon etch processes etch silicon at a high rate, but are not as selective to titanium as desired, and have a tendency to etch into thin titanium layer 22. When this occurs, the etch often breaks through thin titanium layer 22, and into underlying active regions 14a and 14b. As active regions 14a, 14b, and 14c are formed from silicon substrate 10, to which the etch is not selective, the etchant quickly etches into and may substantially deplete underlying active regions 14a, 14b, and 14c. Damage of active regions 14a, 14b, and 14c causes junction degradation, which results in device failure and consequent lower yield rates of the integrated circuit manufacturing process.
A further area where the conventional local interconnect formation process can be improved is in lowering the resistivity of the resulting titanium salicide local interconnects. Titanium salicide, if not properly formed and doped, has an inherent resistivity that lowers electronic device speeds and subsequently, the performance of the completed integrated circuit. High resistivity is also a barrier to miniaturization. Properly forming and doping the titanium salicide, so as to lower resistivity, increases the complexity and cost of the integrated circuit formation process.
Accordingly, from the above discussion, it is apparent that what is needed in the art is a method whereby local interconnects can be formed in a less complex manner, without the tendency to undercut and overetch, and preferably with a lower resistivity in order to increase the speed of the electronic device into which the local interconnects are incorporated.